1. Field of the Invention
The present invention relates to a Built-In Self-Test (BIST) circuit. More specifically, the present invention relates to a BIST circuit and operating method for automated testing of a programmable analog gain stage.
2. Description of the Related Art
Mixed analog-digital signal integrated circuits (ICs) are highly useful for signal processing applications such as signal acquisition and generation including synthesis, filtering, modulation and the like. Design goals of signal processing integrated circuits typically seek a reduction in size and cost. Factors determining the total cost of an integrated circuit include manufacturing costs, silicon area, packaging costs, development costs, test vector development, and testing time.
For high volume production of monolithic mixed-signal integrated circuits, two factors contribute to manufacturing costs. A first factor are the direct costs of test equipment and testing time. A second factor are the indirect costs of test procedure development. Testing costs in mixed-signal integrated circuits are dominated by the costs of analog testing despite the relatively small amount of analog circuitry in comparison to digital logic ("A BIST Scheme for an SNR Test of a Sigma-Delta ADC", Toner M. F. and Roberts G. W., International Test Conference 1993, Paper 37.3, page 805).
Costs are reduced by decreasing testing time. Typically, mixed signal integrated circuits are tested using a two-pass test using a wafer sort, a limited testing of the die while attached to a wafer in a first phase and a class test including full analog and digital testing of a packaged part in a second phase. Unfortunately, the first wafer-sort phase of the two-pass test is generally limited in testing for gross functionality of analog blocks. As a result, some die are packaged with nonfunctional analog circuit sections. The packaged circuits are then tested in the second phase, found to be defective and then scrapped. Wasted test time, scrapped packaging and lower throughput inherent in the conventional two-part testing lead to high production costs.
Testing is performed using mixed-signal test equipment including precision programmable analog signal generators, waveform digitizers, and specialized digital signal processing equipment. The testing is costly because of the usage of expensive test equipment. Production costs of mixed-signal integrated circuits are greatly influenced by efficiency of testing.
Recently, cost reductions have been proposed through usage of built-in self-test (BIST) approaches for testing mixed-signal integrated circuits. BIST techniques are advantageous for reducing production time testing by a manufacturer. BIST techniques are further advantageous if the analog portion of the test is filly integrated into the integrated circuit so that only digital signals are passed from an external tester and the integrated circuit. Current BIST approaches employ simple functional testing involving an analysis of digital data converted from analog signals using an embedded analog-to-digital converter (ADC) at the analog input terminals of a device. The resulting digital data is analyzed using histogram methods to calculate parameters including measures of nonlinearity, differential nonlinearity, bandwidth, noise, dynamic range, harmonic distortion and the like.
These BIST approaches require high accuracy, high volumes of data streams for sufficient testing and still require usage of expensive external test equipment to process and analyze the data stream, resulting in a large amount of test time and high testing costs. Furthermore, these BIST methods require the usage of an accurate embedded ADC for conversion of data. Accurate converters are not implemented in some digital signal processing circuits. The inclusion of an ADC for test purposes alone substantially increases the size and cost of an integrated circuit.
What is needed is a BIST test method and apparatus that reduces or avoids the usage of expensive test equipment and reduces the testing time. What is further needed is a BIST test method and apparatus that does not utilize a complex embedded ADC.